AMP Interrupt Configuration

Interrupt configuration

11.1 Cortex-A GIC

GIC interrupts are divided into:

• SGI: interrupt IDs 0 through 15, generated by software and private to each CPU.
• PPI: interrupt IDs 16 through 31, private to each CPU.
• SPI: interrupt IDs starting at 32, shared between CPUs.

AP RTOS/HAL firmware must consistently configure each peripheral interrupt's priority and target CPU:

#define DEFAULT_IRQ_CPU 1

static struct GIC_AMP_IRQ_INIT_CFG irqsConfig[] = {
    GIC_AMP_IRQ_CFG_ROUTE(GPIO0_IRQn, 0xd0,
                          CPU_GET_AFFINITY(0, 0)),
    GIC_AMP_IRQ_CFG_ROUTE(0, 0,
                          CPU_GET_AFFINITY(DEFAULT_IRQ_CPU, 0)),
};

Interrupts not explicitly listed are routed to DEFAULT_IRQ_CPU. When multiple RTOS/HAL systems share one GIC routing table, each SPI must have exactly one intended handler.

11.2 Cortex-M NVIC and RISC-V IPIC

• Cortex-M uses NVIC. When there are more external interrupt sources than direct NVIC inputs, INTMUX is normally used.
• The RK3568 RISC-V core uses IPIC and can also receive peripheral interrupts through INTMUX.
• HAL_Init() normally initializes NVIC. For RISC-V projects, verify the HAL_INTMUX_Init() and IPIC initialization path.

The complete peripheral interrupt enable sequence is: route the interrupt to the target core → register the ISR → enable the interrupt controller input → enable the peripheral's own interrupt source.